Verification Engineer- Subsystem
Anthriq
- Experience
- 8+ years
- Location
- On-site
- LPDDR4/5/5X
- High-speed interconnect protocols
- DMA engines
- Credit-based flow control
- Arbitration
- Memory-map region protection
- UVM architecture
- Constrained-random stimulus
About the company
Anthriq is a signal processing infrastructure company. We build the full acquisition and compute stack for human-aware technology — from custom analog front-end IP that captures biosignals at the source, to signal-first compute systems built for time-critical, deterministic workloads. Our infrastructure is designed around one principle: the signal should never be the bottleneck. General-purpose processors — CPUs, GPUs, DSPs — were not built for this class of problems. They approximate determinism. We built it in architecture. Anthriq Silicon is our ground-up effort to build a new compute category. Key responsibilities
- Architect UVM testbenches for memory-subsystem wrappers, credit-based flow control, and multi-channel DMA.
- Develop packet-level protocol checkers, retry-buffer FSM monitors, and error-injection benches for a custom die-to-die link layer, incl. cross-die fail-stop.
- Verify hardware synchronization barriers and multi-client arbitration scoreboards.
- Own test-plan execution, mentor junior engineers, drive block coverage to 100%. Must-have skills
- 8+ years verifying memory controllers (LPDDR4/5/5X) or high-speed interconnect protocols and DMA engines.
- Credit-based flow control, arbitration, memory-map region protection.
- UVM architecture, constrained-random stimulus, functional-coverage modeling.
- Link-layer packetization, retry, framing FSM verification.
- Clock-Domain-Crossing (CDC) verification. Nice-to-have
- Multi-die / die-to-die (UCIe-class or proprietary) link experience.
- PHY-to-MAC protocol simulation.
- Target EDA tools: Cadence Xcelium, vManager, Indago
About the role
Deliver 100% block coverage on memory-subsystem and link-layer verification. Ensure reliable, deterministic signal processing infrastructure through thorough verification. Drive verification excellence to support Anthriq's silicon category.
What you’ll do
- Architect UVM testbenches for memory-subsystem wrappers, credit-based flow control, and multi-channel DMA
- Develop packet-level protocol checkers, retry-buffer FSM monitors, and error-injection benches for a custom die-to-die link layer, incl. cross-die fail-stop
- Verify hardware synchronization barriers and multi-client arbitration scoreboards
- Own test-plan execution, mentor junior engineers, drive block coverage to 100%
What we’re looking for
Must have
- LPDDR4/5/5X
- High-speed interconnect protocols
- DMA engines
- Credit-based flow control
- Arbitration
- Memory-map region protection
Nice to have
- Multi-die / die-to-die (UCIe-class or proprietary) link experience
- PHY-to-MAC protocol simulation
- Cadence Xcelium
- vManager
- Indago
Tech stack
- SystemVerilog
- UVM
- SVA (formal verification)
- Design Compiler / Genus (synthesis)
- SDC timing constraints
- Vivado (FPGA prototyping)
- LLVM (compilers)
- custom ISA
- signal processing
About Anthriq
Anthriq (formerly Nexstem) is a venture-backed Bengaluru biotech/neurotech startup building a full-stack biosignal infrastructure platform — a 'Human Body API' — that captures and interprets EEG, ECG, EMG and other electrophysiological signals through integrated hardware, software, and a data foundry to power programmable human-aware technology. It is also running 'Anthriq Silicon,' a ground-up effort to build a new compute category: a custom ISA, a frontier signal-processing chip, and a full toolchain designed alongside the silicon.
Biotechnology / Neurotech / Biosignal infrastructure / Semiconductors · Seed · 11-50 employees (25 as of Aug 31, 2025)