Lead RTL Engineer
Anthriq
- Pay
- ₹30–80 lakh a year
- Experience
- 7–17 years
- Location
- Bangalore · On-site
- Job type
- Full-time
- SystemVerilog
- Synthesis (Design Compiler/Genus)
- Static Timing Analysis (PrimeTime/Tempus)
- Processor/DSP Architecture
- SDC Constraints
About the role
Lead RTL Implementation. Drive Synthesis and Timing Closure. Establish Design Methodology. Coordinate Physical Design Handoff. Code Review and Quality Assurance. Verification Collaboration.
What you’ll do
- Translate high-level architecture specifications into synthesizable SystemVerilog code while leading a team of engineers.
- Own the synthesis flow using Design Compiler or Genus, and drive timing closure to meet aggressive clock targets.
- Define and maintain RTL coding standards, linting rules, and SDC timing constraints for the project.
- Manage the handoff of netlists, constraints, and floorplan guidance to the physical design team or outsource partners.
- Review all RTL code submissions to identify timing hazards, FSM issues, and non-synthesizable patterns.
- Work closely with the verification team to resolve bugs and achieve coverage closure.
What we’re looking for
Must have
- SystemVerilog
- Synthesis (Design Compiler/Genus)
- Static Timing Analysis (PrimeTime/Tempus)
- Processor/DSP Architecture
- SDC Constraints
Nice to have
- VLIW/Vector Processor Design
- Formal Verification (SVA)
- FPGA Prototyping (Vivado)
What makes this role challenging
- Experience managing vendor relationships for physical design
- Understanding of clock domain crossing in multi-core systems
- Ability to define micro-architectural specs from high-level arch
- Cannot explain the difference between setup and hold time violations
- Unfamiliar with writing or debugging SDC constraints
- Has never participated in a tapeout or worked with physical design engineers
- Relies solely on verification team to find bugs without self-checking
Job Description – Lead RTL Engineer About the company: Anthriq is a signal processing infrastructure company. We build the full acquisition and compute
stack
for
human-aware
technology
—
from
custom
analog
front-end
IP
that
captures
biosignals
at
the
source,
to
signal-first
compute
systems
built
for
time-critical,
deterministic
workloads.
Our infrastructure is designed around one principle: the signal should never be the boleneck.
General-purpose
processors
—
CPUs,
GPUs,
DSPs
—
were
not
built
for
this
class
of
problems.
They
approximate
determinism.
We
built
it
in
by
architecture.
Anthriq Silicon is our ground-up eort to build a new compute category. Read More About Anthriq Silicon Program here hps://
About the Role We are building a high-performance signal processing ASIC — a multi-core vector processor with a
custom
ISA,
targeting
defense,
5G,
and
test
&
measurement
markets.
You
will
lead
the
RTL
implementation
from
architecture
spec
to
tapeout-ready
netlist.
This
is
a
hands-on
technical
lead
role.
You
write
RTL,
review
RTL,
and
own
the
synthesis
flow.
You
are
the
bridge
between
the
architect
(who
defines
the
spec)
and
the
RTL
team
(who
implements
it).
Responsibilities
- Translate the architecture specification into synthesizable SystemVerilog
- Own the RTL coding standards, linting rules, and design methodology
- Lead a team of 5-7 RTL engineers through the full design cycle
- Own the synthesis flow (Design Compiler or Genus) and drive timing closure
- Define and maintain SDC timing constraints
- Review all RTL code submissions for correctness, synthesizability, and style
- Coordinate with the outsource partner on GDSII hando (netlist, constraints, floorplan
guidance)
- Work closely with the verification team to resolve bugs and achieve coverage closure
Requirements
- 7+ years of RTL design experience in SystemVerilog
- At least 1 tapeout through to GDSII (not just RTL — you've seen the full flow)
- Synthesis and timing closure experience (Design Compiler or Genus, PrimeTime or
Tempus)
- Processor, DSP, or datapath-heavy design experience
- Familiarity with advanced process nodes (28nm class or below)
- Strong code review skills, you can spot timing hazards, FSM issues, and non-synthesizable
paerns
in
review
- Comfortable leading a small team while remaining hands-on
Nice to have
- VLIW or vector processor design experience
- Experience with deterministic/real-time architectures (no caches, fixed latencies)
- Formal verification awareness (writing SVA, working with formal tools)
- FPGA prototyping experience (Vivado)
To apply:
Please
send
your
application
to